To support the numerous functions provided by modern smartphones and related mobile devices, various system-on-a-chip (SoC) integrated circuits have been developed. An SoC will have a digital core incorporating a microprocessor and related elements such as a graphics processor. In addition, the SoC will need to support various interfaces to external devices such as a double data rate (DDR) memory, a Universal Serial Bus (USB), a high definition multimedia interface (HDMI), or a serializer-deserializer (SerDes) interface.
In contrast to the digital core for an SoC, a SerDes requires assorted analog components that are incorporated into a mixed digital/analog circuit domain. An example SoC 100 including a SerDes interface 105 in a digital/analog circuit domain is shown in FIG. 1. A controller 110 presents data words and control signals to a physical coding sublayer (PCS) circuit 115. A mixed signal digital domain 120 includes a built-in-self-test (BIST) and control circuits for SerDes interface 105. SerDes interface 105 includes a plurality of analog components such as a bandgap circuit (Bias), a phase-locked loop (PLL), electrostatic discharge (ESD) circuitry, and a low drop-out regulator (LDO) that assist in the serialization of data words from controller 110 (after processing through PCS circuit 115) in a transmit path that includes thresholding circuit 140, buffers 125 and a differential transmitter 130. Differential transmitter 130 transmits the serialized data words over a pair of differential output pins TX+ and TX−. Similarly, SerDes interface 105 receives serialized data words from an external source over a pair of differential input tenninals RX+ and RX− at a differential receiver 135. A signal detector (SigDet) monitors the RX+ and RX− to detect for the presence of incoming differential data. The resulting serial data from receiver 135 is equalized in an equalizer and sampled in a sampler responsive to a clock from a clock data recovery (CDR) circuit. An analogous equalizer may be included in the transmit path. A de-serializer deserializes the sampled received data from the sampler so that the received data words may be processed through PCS circuit 115 and presented to controller 110 as received data and control words.
Although such a SerDes interface 105 is conventional, the design of its analog components is becoming more and more difficult at the advanced technology nodes. For example, transmitter 130 and receiver 135 are sensitive to noise. The bandgap reference and the LDO are sensitive to the voltage headroom issues that develop as the power supply voltage is continually decreased at the advanced technology nodes. The PLL design is also problematic in that a high-precision clock is critical for error-free operation of SerDes interface 105. Moreover, analog components in advanced process nodes retain their relatively large size as compared to the digital components and thus consume substantial die area and increase cost. In contrast, the design of the digital core in SoC 100 that includes controller 110 as well as a microprocessor (not illustrated) is less noise sensitive and time consuming to design. Moreover, the digital components consume less die space. The design of SerDes interface 105 is thus becoming a bottleneck as SoC designs are continually updated to newer technology nodes.
Accordingly, there is a need in the art for improved SerDes interfaces.